1. Field of the Invention
The invention relates to computer systems and more particularly to a computer system having a high speed communication link having multiple pipes operating on the communication link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG. 1. One central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus 101 as the connection between the xe2x80x9cnorth bridgexe2x80x9d integrated circuit 103 and the xe2x80x9csouth bridgexe2x80x9d integrated circuit 105. The north bridge functions generally as a switch connecting CPU 107, a graphics bus 109 such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory 111. The north bridge also contains the memory controller function.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the possible exception of video output as illustrated in FIG. 1. Specifically, the south bridge 105 provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus 115, the Integrated Device Electronics (IDE) disk interface 117 and the Universal Serial Bus (USB) 119. In the illustrated prior art architecture, PCI bus 101 also functions as the major input/output bus for add-in functions such as network connection 121. The various busses and devices shown in FIG. 1 are conventional in the personal computer industry and are not described further herein unless necessary for an understanding of the present invention.
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data.
Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to memory and peripherals or bulk data transmissions from a hard drive into system memory.
The PCI bus causes a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput available on the PCI bus for a particular transfer and the latency that is involved for that transfer is unknown. PCI bus load fluctuations can result in uncertain and irregular quality of service. Therefore, having a PCI bus as the major input/output bus means that the major input/output bus of present day computer systems does not provide proper support for both isochronous and asynchronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data may become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance.
In addition, as the number of functions integrated onto the integrated circuits of computer systems increases, the need for additional integrated circuit package pins also increases. Supporting the host bus, the memory interface, the PCI bus and a graphics interface results in a north bridge integrated circuit having a relatively large number of pins that is relatively unpopulated in terms of the number of transistors on the integrated circuit. The large number of pins requires the integrated circuit to be larger than would otherwise be necessary and therefore increases costs.
It would be desirable therefore, to have a deterministic high speed major interconnect bus providing improved quality of service for both isochronous and asynchronous traffic classes. It would also be desirable to reduce the pressure for additional pins on the integrated circuits making up the computer system.
Accordingly, a communication link is provided that can be used both as a primary communication link and can also be used as a subordinate link to connect to other integrated circuits and/or functions. In one embodiment of the invention, a computer system is provided that includes a first integrated circuit having a plurality of first functions, a second integrated circuit having a plurality of second functions, and a first communication link connecting the first and second integrated circuits. The communication link includes a plurality of first logical pipes carrying transactions on the first communication link, each of the first pipes having a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. A second communication link is coupled to the first communication link and includes a plurality of second logical pipes carrying transactions on the second communication link, each of the second logical pipes has a source end and a target end. A target (or source) end of one of the first pipes communicatively coupled on the second integrated circuit to a source (or target) end one of the second pipes.
In another embodiment of the invention, a method is provided for communicating over a first and second communication links in a computer system, the first and second communication links including respectively a first and second plurality of logical pipes carrying transactions in packets. Commands are issued from a source end of the first communication link. The command is transmitted in a command packet over the first communication link. The command packet includes a pipe identification identifying a source and target end of the pipe on which the transaction is being carried. The packet also includes an address field identifying a destination for the command. The information from the command packet is provided to a source end of the second communication link and the information is sent to a target end of the second communication link.